United States Patent 5,742,791
Mahalingaiah, et. al. Apr. 21, 1998

Apparatus for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor

Abstract

A core snoop buffer apparatus is provide which stores addresses of pages from which instructions have been fetched but not yet retired (i.e. the instructions are outstanding within the instruction processing pipeline). Addresses corresponding to memory locations being modified are compared to the addresses stored in the core snoop buffer on a page basis. If a match is detected, then instructions are flushed from the instruction processing pipeline and refetched. In this manner, the instructions executed to the point of modifying registers or memory are correct in self-modifying code or multiprocessor environments. Instructions may be speculatively fetched and executed while retaining coherency with respect to changes to memory. The number of pages from which instructions are concurrently outstanding within the microprocessor are typically small compared to the number of cache lines outstanding or the number of instructions outstanding. Therefore, a relatively small hardware structure may be employed to perform the instruction coherency functionality.


Inventors: Mahalingaiah; Rupaka (Austin, TX); Zuraski, Jr.; Gerald D. (Austin, TX).
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA).
Appl. No.: 601,618
Filed: Feb. 14, 1996
Intl. Cl. : G06F 12/08, G06F 9/38
Current U.S. Cl.: 711/146; 711/3; 711/140; 712/205
Field of Search: 395/473, 467, 496, 381, 395, 569, 403, 468

References Cited | [Referenced By]


U.S. Patent Documents

4,044,338 Aug., 1977 Wolf 365/49
4,453,212 Jun., 1984 Gaither et al. 395/402
4,807,115 Feb., 1989 Torng 395/391
4,858,105 Aug., 1989 Kuriyama et al. 395/582
5,226,126 Jul., 1993 McFarland et al. 395/394
5,226,130 Jul., 1993 Favor et al. 395/585

Foreign Patent Documents

0259095 Mar., 1988 EP  
0381471 Aug., 1990 EP  
0459232 Dec., 1991 EP  
2263985 Aug., 1993 GB  
2263987 Aug., 1993 GB  
2281422 Mar., 1995 GB  
Other References
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Reort, vol. 8, No. 14, Oct. 24, 1994, 7 pages.

Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.

Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.


Primary Examiner: Kim; Matthew M.
Attorney, Agent or Firm: Conley, Rose & TayonKivlin; B. Noel
12 Claims, 4 Drawing Figures


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