United States Patent 6,073,217
Mahalingaiah, et. al. Jun. 6, 2000

Method for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor

Abstract

A core snoop buffer apparatus is provide which stores addresses of pages from which instructions have been fetched but not yet retired (i.e. the instructions are outstanding within the instruction processing pipeline). Addresses corresponding to memory locations being modified are compared to the addresses stored in the core snoop buffer on a page basis. If a match is detected, then instructions are flushed from the instruction processing pipeline and refetched. In this manner, the instructions executed to the point of modifying registers or memory are correct in self-modifying code or multiprocessor environments. Instructions may be speculatively fetched and executed while retaining coherency with respect to changes to memory. The number of pages from which instructions are concurrently outstanding within the microprocessor are typically small compared to the number of cache lines outstanding or the number of instructions outstanding. Therefore, a relatively small hardware structure may be employed to perform the instruction coherency functionality.


Inventors: Mahalingaiah; Rupaka (Austin, TX); Zuraski, Jr.; Gerald D. (Austin, TX).
Assignee: Advanced Micro Devices (Sunnyvale, CA).
Appl. No.: 15,087
Filed: Jan. 29, 1998

Related U.S. Application Data

Division of Ser No. 601,618, Feb. 14, 1996, Pat. No. 5,742,791.
Intl. Cl. : G06F 12/08
Current U.S. Cl.: 711/146; 711/141; 711/142; 711/143; 711/144
Field of Search: 711/3, 141, 142, 143, 144, 146, 140

References Cited | [Referenced By]


U.S. Patent Documents

4,044,338 Aug., 1977 Wolf 365/49
4,453,212 Jun., 1984 Gaither et al. 711/221
4,807,115 Feb., 1989 Torng 712/215
4,858,105 Aug., 1989 Kuriyama et al. 712/235
5,226,126 Jul., 1993 McFarland et al. 712/218
5,226,130 Jul., 1993 Favor et al. 712/238
5,276,828 Jan., 1994 Dion 395/200.78
5,652,859 Jul., 1997 Mulla et al. 711/146
5,742,791 Apr., 1998 Mahalingaiah et al. 711/146

Foreign Patent Documents

0259095 Mar., 1988 EP  
0381471 Aug., 1990 EP  
0459232 Dec., 1991 EP  
2263985 Aug., 1993 GB  
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Other References
Slater, M., "AMD's Microprocessor K5 designed to Outrun Pentium" (Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.

Rupley, et al, "P6: The Next Step?" PC Magazine, Sep. 12, 1995, 16 pages.

Halfhill, "AMD K6 Takes on Intel P6, " BYTE Magazine, Jan. 1996, 4 pages.


Primary Examiner: Chan; Eddie P.
Assistant Examiner: Nguyen; Than
Attorney, Agent or Firm: Conley, Rose & Tayon, PCKivlin; B. Noel, Merkel; Lawrence J.
7 Claims, 4 Drawing Figures


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