| United States Patent | 6,134,650 |
| Zuraski, Jr., et. al. | Oct. 17, 2000 |
Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data
Abstract
A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. When the cache line is scanned for dispatch, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the location of the first scanned instruction and the functional bits of the predecode data to multiplex instruction specific bytes of the first scanned instruction to the MROM unit. If the first scanned instruction is not the first microcode instruction, then in a subsequent clock cycle, the first microcode instruction is dispatched the MROM unit and the mispredicted instruction is canceled.
| Inventors: | Zuraski, Jr.; Gerald D. (Austin, TX); Southard; Shane (Cedar Park, TX); Calle; Mauricio (Austin, TX). |
| Assignee: | Advanced Micro Devices, Inc. (Sunnyvale, CA). |
| Appl. No.: | 989,262 |
| Filed: | Dec. 12, 1997 |
| Intl. Cl. : | G06F 9/38 |
| Current U.S. Cl.: | 712/213; 712/210; 712/212 |
| Field of Search: | 712/213, 210, 212, 204 |
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Foreign Patent Documents
| 0651322A1 | May, 1995 | EP |
Primary Examiner: An; Meng-Ai T.
Assistant Examiner: Patel; Gautam R.
Attorney, Agent or Firm: Conley, Rose & Tayon, P.C.Merkel;
Lawrence J.
17 Claims, 15 Drawing Figures
Last Updated : Sun Mar 9 23:19:03 EST 2008
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