Method and apparatus for built-in self-repair of memory storage arrays

Abstract

An integrated circuit device includes a memory array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns. First and second redundant rows of memory cells and a first redundant column of memory cells are provided. A test circuit is coupled to the memory array and is adapted to test a plurality of memory cells coupled to each of the plurality of rows. A control circuit is coupled to the test circuit and is adapted to receive test results from the test circuit, the control circuit being adapted to respond to a detection of a defective memory cell to determine an assignment of at least one of the first and second redundant rows and first redundant column. A first register is coupled to the control circuit and adapted to receive an assignment of the first redundant row in response to a determination by the control circuit, a second register is coupled to the control circuit and adapted to receive an assignment of the first redundant column in response to a determination by the control circuit, and a third register is coupled to the control circuit and adapted to receive an assignment of the second redundant row in response to a determination by the control circuit.

References Cited [Referenced By]

U.S. Patent Documents

Primary Examiner: Phan; Trong
Attorney, Agent or Firm: Williams, Morgan & Amerson, P.C.

Last Updated : Sun Mar 9 23:17:03 EST 2008