United States Patent 6,260,134
Zuraski, Jr. ,   et al. July 10, 2001

Fixed shift amount variable length instruction stream pre-decoding for start byte determination based on prefix indicating length vector presuming potential start byte

Abstract

A predecode unit is configured to predecode a fixed number of instruction bytes of variable length instructions per clock cycle. The predecode unit outputs predecode bits which identify the start byte of an instruction. An instruction alignment unit uses the start bits to dispatch the instructions to a plurality of decode units that form fixed issue positions. In one embodiment, the predecode unit identifies a plurality of length vectors. Each length vector is associated with one of the instruction bytes predecoded in a clock cycle and identifies the length of an instruction if an instruction starts at the instruction byte corresponding to the length vector. A tree circuit determines in which instruction bytes instructions start.


Inventors: Zuraski, Jr.; Gerald D. (Austin, TX); Ahmed; Syed F. (Austin, TX); Miller; Paul K. (McKinney, TX)
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Appl. No.: 184750
Filed: November 2, 1998
Current U.S. Class: 712/210; 712/204; 712/213
Intern'l Class: G06F 009/38
Field of Search: 712/204,210,213

References Cited [Referenced By]


U.S. Patent Documents

5586277 Dec., 1996 Brown et al. 712/210.
5619666 Apr., 1997 Coon et al. 712/208.
5758116 May., 1998 Lee et al. 712/210.
5809272 Sep., 1998 Thusoo et al. 712/210.
5809273 Sep., 1998 Favor et al. 712/210.
5819059 Oct., 1998 Tran 712/213.
5822558 Oct., 1998 Tran 712/213.
5845099 Dec., 1998 Krishnamurthy et al. 712/204.
5941980 Aug., 1999 Shang et al. 712/204.
5948096 Apr., 1999 Ginosar et al. 712/210.
Foreign Patent Documents
0 417 013 Mar., 1991 EP.  


Primary Examiner: Kim; Kenneth S.
Attorney, Agent or Firm: Conley, Rose & Tayon, PC, Christen; Dan R.


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