| United States Patent | 6,415,360 |
| Hughes , et al. | July 2, 2002 |
Minimizing self-modifying code
checks for uncacheable memory types
Abstract
A processor employs an SMC check apparatus. The SMC check apparatus may minimize the number of explicit SMC checks performed for non-cacheable stores. Cacheable stores may be handled using any suitable mechanism. For non-cacheable stores, the processor tracks whether or not the in-flight instructions are cached. Upon encountering a non-cacheable store, the processor inhibits an SMC check if the in-flight instructions are cached. Since, for performance reasons, the code stream is often cached, non-cacheable stores may frequently be able to skip an explicit, complex, and time consuming SMC check. Performance of non-cacheable stores (and memory throughput overall) may be increased. The handling of non-cacheable stores as described herein may be particularly beneficial to video data manipulations, which may frequently be of a non-cacheable memory type and which may be important to the overall performance of a computer system.
| Inventors: | Hughes; William Alexander (Burlingame, CA); Lewchuk; William Kurt (Austin, TX); Zuraski, Jr.; Gerald D. (Austin, TX) |
| Assignee: | Advanced Micro Devices, Inc. (Sunnyvale, CA) |
| Appl. No.: | 314066 |
| Filed: | May 18, 1999 |
| Current U.S. Class: | 711/139; 711/138 |
| Intern'l Class: | G06F 012/00 |
| Field of Search: | 711/138,139,118,125,126 |
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| Foreign Patent Documents | |||
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Other References |
Leibholz et al., "The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor," .COPYRGT.1997 IEEE, pp. 28-36. |
Primary Examiner: Kim; Matthew
Assistant Examiner: Vital; Pierre M.
Attorney, Agent or Firm: Conley, Rose & Tayon, PC,
Merkel; Lawrence J.
Last Updated : Sun Mar 9 23:09:03 EST 2008
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